1. Field of the Invention
The present invention relates to a shift register circuit, and more particularly, to a shift register circuit having high driving ability.
2. Description of the Prior Art
Liquid crystal displays (LCDs) have advantages of a thin profile, low power consumption, and low radiation, and are broadly adopted for application in media players, mobile phones, personal digital assistants (PDAs), computer displays, and flat screen televisions. The operation of a liquid crystal display is featured by modulating the voltage drop across opposite sides of a liquid crystal layer for twisting the angles of liquid crystal molecules in the liquid crystal layer so that the transmittance of the liquid crystal layer can be controlled for illustrating images with the aid of light source provided by a backlight module. In general, the liquid crystal display comprises plural pixel units, a source driver, and a shift register circuit. The source driver is utilized for providing plural data signals to be written into the pixel units. The shift register circuit comprises a plurality of shift register stages and functions to generate plural gate signals for controlling the operations of writing the data signals into the pixel units. That is, the shift register circuit is a crucial device for providing a control of writing the data signals into the pixel units.
FIG. 1 is a schematic diagram showing a prior-art shift register circuit. As shown in FIG. 1, the shift register circuit 100 comprises a plurality of shift register stages and, for ease of explanation, illustrates an (N−1) th shift register stage 111, an Nth shift register stage 112 and an (N+1) th shift register stage 113. Each shift register stage is employed to generate one corresponding gate signal furnished to one corresponding gate line according to a gate signal generated by one preceding shift register stage. For instance, the (N−1) th shift register stage 111 is utilized for generating a gate signal SGn−1 furnished to a gate line GLn−1 according to a gate signal SGn−2, the Nth shift register stage 112 is utilized for generating a gate signal SGn furnished to a gate line GLn according to the gate signal SGn−1, and the (N+1)th shift register stage 113 is utilized for generating a gate signal SGn+1 furnished to a gate line GLn+1 according to the gate signal SGn. In the operation of the Nth shift register stage 112, the input transistor 181 of an input unit 180 comprises a first end for receiving the gate signal SGn−1, a gate end for receiving a control signal, and a second end for outputting a driving control voltage VQn. As the gate signal SGn−1 and the control signal are both at a high-level voltage, the second end of the input transistor 181 outputs the driving control voltage VQn which is lower than the high-level voltage by the threshold voltage of the input transistor 181. Thereafter, the driving control voltage VQn is further pulled up to an active voltage by the rising edge of a system clock CK through coupling of the device capacitor of a pull-up transistor 191 in a pull-up unit 190. The active voltage is then employed to drive the pull-up unit 190 for generating the gate signal SGn. However, the active voltage is lower than twice the high-level voltage by the threshold voltage of the input transistor 181. That is, the output driving ability of the pull-up unit 190 is significantly lowered by the threshold voltage of the input transistor 181 in the operation of the Nth shift register stage 112.